Advanced Defect Modeling and Testing Technical Manager

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers' products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world's largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.

We are seeking an experienced Technical Manager to join our team researching advanced defect modeling, testing, screening, and analysis for next-generation semiconductor processes and 3D packaging technologies. This role is strategically critical for TSMC: it represents a multi-year journey to pioneer new approaches to defect modeling in advanced packaging. Defect modeling in this space is still an emerging discipline, with global leaders actively defining the standards. This position provides a unique opportunity to keep TSMC at the forefront of innovation and shape the methodologies that will guide the industry.

The successful candidate will develop methodologies and tools to model and simulate defects, assess their impact on performance, optimize testing strategies, and innovate beyond the limitations of current testing instruments. This engineer will collaborate across design, process, test, and reliability functions to ensure the functionality and yield of advanced 2.5D/3D packaging technologies.

Job Responsibilities:

1. Defect Modeling & Analysis: Develop defect models for 2D structures (standard cells, FEOL/MEOL/BEOL layers) and 3D structures such as TSVs, interconnects, hybrid bonding, and chip stacking. Perform root-cause analyses of electrical, mechanical, and thermal defects in advanced packages and address them using design-for-test methods.

2. Simulation & ATPG: Conduct SPICE simulations to evaluate circuit behavior under defect conditions and identify failure scenarios. Use EDA ATPG tools (or develop internal methods) to generate defect-oriented test patterns. A strong understanding of standard cell layout, parasitic extraction, and simulation is required.

3. Testing & Probing Structures: Assess the influence of probing techniques and test structure designs on defect detection and reliability learning. Develop and implement methodologies leveraging test/probe structures to monitor process variations and enhance yield. Collaborate closely with internal partners (Standard Cell team, Product team, Fab, and Q&R) and external partners (EDA vendors).

4. Research & Optimization: Implement advanced test methodologies for defect detection at both chip and packaging levels. Stay updated on evolving technologies and defect mechanisms in semiconductor manufacturing. Contribute to patents and publications in leading conferences and journals.

5. Cross-Functional Collaboration: The role demands a proactive mindset and flexibility to push solutions forward across geographies and stakeholders.

Job Qualifications:

1. Master's or Ph.D. degree in Computer Engineering, Semiconductor Physics, or a related field.

2. At least 15+ years of expertise in failure mechanisms, defect physics, testing, or reliability analysis for semiconductor devices, including 2D and 3D structures.

3. Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and DFT/ATPG methodologies for packaging and advanced nodes.

4. Programming or scripting skills (Python, Perl, C++) for automation and data analysis are required; experience with AI/ML for defect prediction is a plus.

5. Deep understanding of defect physics, testing/probing structures, and their impact on defect detection, characterization, and yield learning in advanced process nodes and 3D packaging. Familiarity with thermal and mechanical considerations in 3D integration.

6. Demonstrated contributions through patents, publications, or conference presentations in defect modeling, reliability, or advanced packaging.

Fostering a global inclusive workplace reflects TSMC's core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.