Principal Package Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at

Overview:
Astera Labs Inc. is a fabless semiconductor company that develops purpose-built connectivity solutions to remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning. To support our rapid growth, we are hiring a Lead IC Package Designer with extensive experience in complex ASIC package design using Cadence APD. Background in SI/PI is a plus.

Job Description:

As an Astera Labs Lead Package Design Engineer, you will take ownership of package design and layout for Astera Labs' portfolio of connectivity products deployed by the world's leading cloud service providers and server/networking OEMs. You will be responsible for driving package substrate design from definition to tape-out, including performance optimization, design for manufacturing, and sign-off verification. You will also provide technical guidance within the package design team: mentoring junior designers, guiding best practices in APD, reviewing design work for quality and consistency, and working closely with SI/PI, product engineering, and hardware teams to ensure first-pass success. You will also help shape design flows, champion productivity improvements, and represent package design expertise in cross-functional discussions.

Basic Qualifications:

• BS/MS in Engineering (Electrical, Mechanical, Materials Science, Physics, or related field).
• 8+ years of experience in Cadence APD/SiP with a track record of independently designing and releasing FCBGA/FCCSP packages from concept to tape-out.
• Proven experience leading package design efforts, reviewing and mentoring other designers, and setting technical directions.
• Deep understanding of BGA substrate technologies, stackups, design rules, and assembly processes.
• Familiarity with package reliability, SI/PI, and design sign-off methodologies.
• Entrepreneurial, open-minded, and hands-on work ethic with the ability to drive multiple priorities in a dynamic environment.
• Strong collaboration and communication skills to work effectively across functions and influence outcomes.

Required Experience:

• Expert proficiency in Cadence APD/SiP (this is a must have). Able to design large-body BGAs from concept through tape-out with minimal guidance.
• Strong knowledge of package BOM integration, layer stackup, padstacks, constraint setup (physical and electrical), SMT component design, and optimization based on SI/PI feedback.
• Experience running and interpreting DRC/DRV/LVS/DFM checks, generating documentation, and releasing Gerbers/artwork.
• Ability to conduct feasibility studies such as fan-out, mock-ups, and layer/package size reduction.
• Understanding of package manufacturing flow, supply chain considerations, reliability, and risk management.
• Technical leadership in driving new APD design flows, methodologies, and automation (working with vendors or through scripting).

 Preferred Experience:

• Multi-chip, interposer, 2.5D or heterogeneous package design experience is a plus.
• Proficiency in scripting languages for design and reporting automation is a plus.

The base salary range is $175,750.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.