PCIE Digital Designer

2 weeks ago

Hsinchu City, Taiwan Morgan Philips Group Full time NT$2,000,000 - NT$2,500,000 per year

Key Responsibilities:

  • Define block-level micro-architecture and develop detailed design specifications.
  • Implement RTL designs while optimizing for power, area, and timing constraints.
  • Collaborate with the Verification team to ensure functional correctness.
  • Work closely with the Backend team to drive the ASIC development process to successful tape-out.
  • Partner with Firmware teams to develop APIs and support silicon bring-up.
  • Perform post-silicon validation and debugging.

Minimum Qualifications:

  • Master's degree in Electrical Engineering or a related field.
  • At least 3 years of industry experience in ASIC design.
  • Strong expertise in micro-architecture and RTL design for complex blocks.
  • Proficiency in RTL design using Hardware Description Languages (HDL).
  • Familiarity with industry-standard design and verification tools (e.g., VCS, Verdi, Design Compiler, etc.).
  • Hands-on experience in the full ASIC design flow, including RTL design, verification, linting, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, gate-level simulations (GLS), ECO, bring-up, and lab debugging.
  • Proficiency in at least one scripting language (Python, TCL, Shell, or Perl).
  • Strong analytical, problem-solving, and teamwork skills.

Preferred Qualifications:

  • Hands-on experience with PCIe logical, link, and transaction layers.
  • Deep understanding of PCIe and CXL protocol stacks, particularly the latest generations.
  • Experience with SerDes architectures.
  • Background in Digital Signal Processing (DSP).
  • Strong debugging and troubleshooting skills.

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