Physical Design Manager

2 weeks ago

Taipei Taipei City, Taiwan Alchip Technologies Full time NT$1,200,000 - NT$3,600,000 per year
  1. Responsible for the digital back-end physical implementation from netlist to GDS, completing the chip sign-off process.
  2. Complete the full-chip floor planning, including chip partitioning, power and ground network, placement of critical modules, utilization optimization, pin assignment.
  3. Complete the overall digital back-end design of the chip, including placement, clock tree implementation, timing closure, power calculation, IR drop analysis, SI closure, and physical verification.
  4. Co-work with front-end design team for the logic, clock and timing optimization.
  5. Co-work with package team for the substrate design and SIPI simulations.

◆ Education:

  • Bachelor's degree or above, majoring in electrical engineering related to microelectronics, integrated circuits, electronic information, etc.
  • 5-8 years or above experience in digital backend related work; Experience in advanced process nodes below 7nm is preferred.
  • Have complete experience in chip tape out and be able to solve complex problems.
  • Strong programming skills in TCL, Python, Perl, shell, etc.
  • Good communication and smooth English reading and writing skills.

◆ Working Experience:

  1. Experienced in tape-out of large chips using mainstream advanced process nodes such as 7nm and 5nm.
  2. Has a proven track record and extensive experience in back-end design, including logic synthesis, design planning, placement and routing, timing analysis, power integrity analysis, and physical verification.
  3. Thorough understanding of global clock distribution and structures, especially in scenarios with multiple voltage domains and multiple clocks.
  4. Unique insights into physical verification with the ability to quickly iterate and optimize flows.
  5. Be familiar with the structure, floorplan, placement and routing, timing closure of high-speed interface IPs, such as DDR5/4, PCIE gen5 or gen4, Serdes and HBM PHY.
  6. Comprehensive understanding of concepts and characteristics of formal verification, low power, UPF, reliability, SI, and noise.
  7. Possesses strong teamwork and communication skills, with the ability to quickly integrate into the team and company culture.
  8. Capable of handling multiple projects simultaneously with high pressure.

◆ Professional Knowledge:

  1. Proficient in EDA tools such as Primetime, StarRC, Fusion Compiler, Innovus, Calibre, Redhawk, etc.
  2. Strong problem-solving skills, with extensive scripting experience in Perl, TCL, Python, etc.

◆ Other Special Requirement:

  1. Fluent English is a plus.

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