Multimedia Digital Design Engineer, Silicon
1 day ago
Google welcomes people with disabilities.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- Experience with a scripting language like Perl or Python.
- Experience with Application-Specific Integrated Circuit (ASIC) or FPGA design verification, synthesis, timing/power analysis and Design for Testing (DFT).
- Knowledge of high performance and low power design techniques, assertion-based formal verification, FPGA and emulation platforms and SOC architecture.
- Knowledge of memory compression, fabric, coherence, cache, or Dynamic Random Access Memory (DRAM).
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Define the block level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
- Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing/power closure, and Field-programmable Gate Array (FPGA)/silicon bring-up.
- Participate in test plan and coverage analysis of the block and ASIC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
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