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Sr. Design Verification Engineer

5 hours ago

Hsinchu City, Taiwan Robert Walters Full time

Overview We are looking for a Senior Digital Verification Engineer to join a collaborative semiconductor design team. This role focuses on top-level and block-level digital verification for advanced digital and mixed-signal designs, working closely with design engineers to ensure full functional compliance and high-quality delivery. Responsibilities * Lead and manage digital verification environments for complex semiconductor designs * Define verification methodologies, review specifications, and develop comprehensive test plans * Perform RTL review, debug simulation issues, and resolve functional bugs * Design digital sub-blocks and support system-level integration * Develop analog models using Cadence Virtuoso and support mixed-signal verification * Create block-level and system-level SystemVerilog assertions * Import and enhance existing UVM environments to improve verification efficiency

Requirements

  • B.S. in Electrical Engineering with 10+ years, or M.S. with 7+ years of digital verification experience
  • Strong experience in SystemVerilog, UVM, and functional verification across multiple products
  • Hands-on experience with Cadence Virtuoso and AMS simulation environments
  • Familiarity with mixed-signal verification and analog schematic exploration
  • Proven ability to debug complex simulation issues
  • Scripting skills (Python, TCL, or csh) are a plus
  • Strong communication skills and ability to work collaboratively in distributed teams

What We Offer

  • Flexible working arrangements
  • Ongoing training and professional development
  • Supportive, inclusive, and technically strong team environment