Principal Engineer

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Job Description:

We are seeking a highly motivated and experienced Principal Packaging Engineer to join our NPI Packaging team. You will be a member of the FPGA (Field Programmable Gate Array) Business Unit, which is a leader in research, development, and manufacturing of highly reliable non-volatile Field Programmable Gate Arrays. In this role, the candidate will be responsible for advanced semiconductor package development. The ideal candidate will have a background in semiconductor packaging and assembly, and a strong ability to collaborate cross-functionally, solve technical problems, and manage projects.

Responsibilities

• Co-design packages with Silicon, Packaging, and Systems engineering teams to ensure designed packages meet electrical, mechanical and thermal requirements of high-performance flip chip packages.
• Work with business unit's IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability for new FPGA devices, satisfying business unit's roadmap for new products.
• Learn and define assembly BOM, process, troubleshoot, and support packaging issues of new advanced technology.
• Create package design documentation and assembly instructions.
• Participate in package technology development and/or other business productivity projects which have broad team impact (e.g. assembly process enhancement, new technology/structure development etc.)
• Manage package qualification for commercial and automotive applications.
• Coordinate with assembly vendors on new packages from development to high volume production.

Requirements/Qualifications:

• Bachelor's or Master's Degree in Electrical or Mechanical Engineering­­.
• Minimum of 10 years of professional experience, including at least 5 years focused on semiconductor IC packaging.
• Well versed with mid-range pin count packaging solutions, including but not limited to organic and ceramic flip chip BGA/LGA,WLCSP, wire bond BGA, and CSP.
• Strong understanding of materials as related to chip packaging interaction.
• Familiar with wafer BEOL (top metal, passivation, UBM, bumping etc.).
• Strong knowledge of advanced substrate manufacturing/process.
• Knowledgeable in JEDEC, AEC and IPC requirements for component and board level reliability qualification.
• Proven project management, communication, and leadership skills.
• Willingness and ability to grow expertise in multiple disciplines, including manufacturing/quality, materials, electrical, thermal, and mechanical engineering.
• Strong technical skills in resolving customer issues related to IC package quality and reliability
• Travel up to 10% is expected.

Preferred Qualifications

• Experience with Ansys Electronic Desktop
• Knowledgeable with failure analysis techniques on package technologies
• Experience with Cadence APD and AutoCad for custom substrate design.  

Travel Time:

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