ASIC Design Engineer, Camera ASIC Team
1 day ago
#ASICTW
Key job responsibilities
-Evaluate 3rd party IP blocks
-Estimate power, performance, and area for significant IPs early in design cycle
-Execute on design specifications to deliver high quality Verilog RTL
-Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA
-Work with pre-silicon verification teams to assist in defining test-plans/test-benches
-Work with post-silicon validation teams to define and execute on test-plans
-Write high quality documents to guide a scalable team
- Bachelor's degree in Electrical Engineering or a related field
- Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
- -Experience in Verilog digital design and debug
- -Experience with Lint, CDC and Logic Equivalency
- -Experience with Synthesizing designs
- -Strong written and verbal skills
- -Experience writing and reviewing design specifications
- Master's degree in Electrical or Communications Engineering or a related field
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