Principal Engineer, AMS Verification
2 days ago
The successful candidate shall possess abundant experience in designing complex DSP for communication systems. You shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication SoCs.
- Model the circuit blocks and mixed-signal IPs, including but not limited to high-speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system-level performance.
- Perform the functional verification and timing analysis on the IPs and the blocks.
- Work with the digital verification team to generate the adequate interface to ensure the timing and connectivity.
- Performs co-simulations on analog blocks and digital blocks in the mixed-signal simulation environment.
You have:
- Has intimate knowledge of UVM verification flow.
- Have prominent tracking record in modeling and verification of analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems.
- Hands-on in modeling and simulating with System-Verilog (WREAL), Verilog-AMS, and/or C, C++.
- Have a decent understanding in CMOS analog / mixed signal design.
- M.S. in E.E. with 5-8 years' experience, or Ph.D. in E.E. with 3-6 years' experience
It would be nice if you also had:
- Able to create IBIS-AMI model.
- Can code in System-Verilog (WREAL).
- Fluent in verbal and written communications.
- Independently resolves issues and conquer design challenges.
- Self-motivated and detail oriented.
- Has good interpersonal skills.
歡迎身障求職者
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