DRAM PHY Designer, up to Sr. Staff

Company:Qualcomm Semiconductor LimitedJob Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:Qualcomm Overview:Qualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform high performance AI and connected computing potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.General Summary:Job Overview:The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of PHY and IO design for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will develop high-speed PHY that connects compute and memory bus in memories to the various channels in the package, interposers, and board that connects memory to compute and memory pools. The candidate should have good knowledge of high-speed and low-energy memory PHY design. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. Responsibilities:Architect, design, and implement high-speed PHY circuitsCreate layouts that optimize circuit placement, signal routing, and power deliveryDevelop robust power delivery to the PHY designSimulate signal integrity and SNR performance together with the package and board s-parameter modelSimulate pre-layout and post-layout mixed-mode circuits under PVT cornersIncorporate power management features to reduce energy consumptionUse state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readinessDevelop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloadsFloorplan PHY circuits under manufacturing constraints, testability, repairability, and high performanceMinimum Qualifications:Knowledge of timing circuits such as DLL, PLLKnowledge of analog building blocksKnowledge of SERDES, phase and duty cycle adjustment circuitsKnowledge of LPDDR, HBM, and IO interfacesKnowledge of eye diagram and noise sourcesMaster's or Ph.D. in Electrical Engineering and a related fieldPreferred Qualifications: Familiar with package designExperience in scripting language (Perl/Python)Familiar with the DRAM datasheets and IO interfacesSoft Skills:Self-Starter with good communication skills and team-working spiritStrong problem-solving and analytical skillsAbility to work independently and as part of a teamMinimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. ORMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. ORPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability- or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. 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