Job Description:

We are seeking a skilled Design Verification Engineer to join our team. In this role, you will work closely with CPU designers, compiler team, performance team, and system verification team to generate test cases automatically. Your responsibilities will include establishing a highly scalable and reusable constrained random test bench that produces coverage-driven tests.

Key Responsibilities:

• Review product definitions and specifications from a verification perspective and collaborate with the design team on feature specifications, test plans, and failure analysis.

• Develop checkers and assertions to verify memory subsystem designs with interconnect.

• Develop tools, test benches, and test suites (UVM, C++/C) to execute test plans.

• Develop and maintain an in-house Verification IP tailored for memory subsystem and interconnect testing.

• Analyze functional coverage, identify holes, and develop solutions to close them.

Requirements:

• A minimum of 3+ years of experience with standard verification tools and methodologies (SystemVerilog/UVM, Verdi/DVE).

• Familiarity with the AMBA protocol is a plus.

• A solid understanding of processor and SoC architecture.

• A thorough understanding of the high-level verification flow methodology.

• Proficient in troubleshooting and possessing strong analytical capabilities.

• Good interpersonal skills to influence people from different disciplines.

Benefits:

We offer a competitive compensation package that includes flexible working hours, generous time-off policy, employee stock option program, pension scheme, and more.

SiFive is committed to creating an inclusive environment for all employees and provides equal employment opportunities. We celebrate diversity and believe it's essential for innovation and growth.

This position requires successful background checks and satisfactory proof of eligibility to work in Taiwan. Any offer of employment is contingent upon obtaining necessary export licenses or approvals.